4.3. POM AXI Lite interface memory map

The POM hardware runtime includes an optional AXI Lite interface to access internal debug registers (read-only). The mapped address space is 16KB (14-bit addresses).

The available registers and their respective addresses are (size in bytes):

Register name	Address	Size	Description
COPY_OPT_IN	0x0	4	Number of copy in optimizations in the command in queue (both internal and external)
COPY_OPT_OUT	0x4	4	Number of copy in optimizations in the command in queue (both internal and external)
ACC_AVAIL	0x8	8	One bit per accelerator, indicating the availability status
QUEUE_NEMPTY	0x10	8	One bit per accelerator, indicating if the internal queue is not empty
CMD_IN_N_CMDS	0x800	4 per acc	For each accelerator, the number of commands it has received
CMD_OUT_N_CMDS	0x900	4 per acc	For each accelerator, the number of commands it has issued
ACC_AVAIL_COUNT	0xA00	8 per acc	For each accelerator, the total number of execution cycles

4.3.1. How to enable the AXI Lite interface

You can enable it with the --enable_pom_axilite flag in AIT. For a full list of AIT options, see AIT options

4.3.2. How to read the registers with QDMA

You can use the script located in the https://pm.bsc.es/gitlab/ompss-at-fpga/rtl/meep-ompss-fpga-cluster repo, under scripts/axilite_cntrl.py.

python3 $MEEP-OMPSS-FPGA-CLUSTER/scripts/axilite_cntrl.py --read_pom

The script needs the XTASKS_PCI_DEV variable.

If you are using OMPIF, you can read all registers, including the message sender and receiver, with the cluster.json file.

python3 $MEEP-OMPSS-FPGA-CLUSTER/scripts/axilite_cntrl.py --cluster cluster.json

If some FPGAs are on remote nodes, the script automatically launches servers on each remote node. However, you need to have the xtasks_devs_$(hostname).sh files in the current working directory.