- Oct 25, 2024
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Rodrigo Arias Mallo authored
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Rodrigo Arias Mallo authored
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Rodrigo Arias Mallo authored
It is faster then Gzip and available in MEEP FPGA cluster.
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Rodrigo Arias Mallo authored
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Rodrigo Arias Mallo authored
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The network is still not working automatically, but the eth0 device is present in the host. Reviewed-by: Rodrigo Arias Mallo <rodrigo.arias@bsc.es>
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- Oct 11, 2024
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Rodrigo Arias Mallo authored
Lagarto OX support See merge request rarias/nixos-riscv!1
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Rodrigo Arias Mallo authored
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Rodrigo Arias Mallo authored
This may be used by another script to determine where we managed to boot.
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Rodrigo Arias Mallo authored
No need to run the SPEC benchmarks all the time. Stopping at the stage2 shell is enough to test most of the system.
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Rodrigo Arias Mallo authored
We use the ENABLE_SPI toggle to also set the PLIC number of inputs.
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Rodrigo Arias Mallo authored
Now we can see jobs from other users.
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Rodrigo Arias Mallo authored
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Rodrigo Arias Mallo authored
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- Oct 10, 2024
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Rodrigo Arias Mallo authored
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Rodrigo Arias Mallo authored
It seems to be hanging now in LVM.
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Rodrigo Arias Mallo authored
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Rodrigo Arias Mallo authored
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Rodrigo Arias Mallo authored
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Rodrigo Arias Mallo authored
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- Oct 09, 2024
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Rodrigo Arias Mallo authored
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Rodrigo Arias Mallo authored
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Rodrigo Arias Mallo authored
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- Oct 08, 2024
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Rodrigo Arias Mallo authored
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Rodrigo Arias Mallo authored
The one contained in the CPU SPEC ISO is built for x86, and there is no binary for RISC-V.
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Rodrigo Arias Mallo authored
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- Oct 07, 2024
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Rodrigo Arias Mallo authored
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Rodrigo Arias Mallo authored
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Rodrigo Arias Mallo authored
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Rodrigo Arias Mallo authored
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Rodrigo Arias Mallo authored
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- Oct 04, 2024
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Rodrigo Arias Mallo authored
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Rodrigo Arias Mallo authored
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Rodrigo Arias Mallo authored
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Rodrigo Arias Mallo authored
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Rodrigo Arias Mallo authored
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Rodrigo Arias Mallo authored
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Rodrigo Arias Mallo authored
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Rodrigo Arias Mallo authored
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- Oct 02, 2024
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Rodrigo Arias Mallo authored
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